Module core::core_arch::aarch64::neon

🔬This is a nightly-only experimental API. (stdsimd #48556)

Available on AArch64 only.

ARMv8 ASIMD intrinsics

Re-exports

• pub use self::generated::*;
  Experimental

Modules

• generated 🔒 Experimental

Structs

• float64x1_t
  ARM-specific 64-bit wide vector of one packed f64.
• float64x1x2_t
  ARM-specific type containing two float64x1_t vectors.
• float64x1x3_t
  ARM-specific type containing three float64x1_t vectors.
• float64x1x4_t
  ARM-specific type containing four float64x1_t vectors.
• float64x2_t
  ARM-specific 128-bit wide vector of two packed f64.
• float64x2x2_t
  ARM-specific type containing two float64x2_t vectors.
• float64x2x3_t
  ARM-specific type containing three float64x2_t vectors.
• float64x2x4_t
  ARM-specific type containing four float64x2_t vectors.

Functions

• vabs_s64_ 🔒 ^⚠Experimental
• vabsd_s64_ 🔒 ^⚠Experimental
• vabsq_s64_ 🔒 ^⚠Experimental
• vaddlv_s8_ 🔒 ^⚠Experimental
• vaddlv_u8_ 🔒 ^⚠Experimental
• vaddlvq_s8_ 🔒 ^⚠Experimental
• vaddlvq_u8_ 🔒 ^⚠Experimental
• vaddv_s8_ 🔒 ^⚠Experimental
• vaddv_s16_ 🔒 ^⚠Experimental
• vaddv_s32_ 🔒 ^⚠Experimental
• vaddv_u8_ 🔒 ^⚠Experimental
• vaddv_u16_ 🔒 ^⚠Experimental
• vaddv_u32_ 🔒 ^⚠Experimental
• vaddvq_s8_ 🔒 ^⚠Experimental
• vaddvq_s16_ 🔒 ^⚠Experimental
• vaddvq_s32_ 🔒 ^⚠Experimental
• vaddvq_s64_ 🔒 ^⚠Experimental
• vaddvq_u8_ 🔒 ^⚠Experimental
• vaddvq_u16_ 🔒 ^⚠Experimental
• vaddvq_u32_ 🔒 ^⚠Experimental
• vaddvq_u64_ 🔒 ^⚠Experimental
• vmaxv_f32_ 🔒 ^⚠Experimental
• vmaxv_s8_ 🔒 ^⚠Experimental
• vmaxv_s16_ 🔒 ^⚠Experimental
• vmaxv_s32_ 🔒 ^⚠Experimental
• vmaxv_u8_ 🔒 ^⚠Experimental
• vmaxv_u16_ 🔒 ^⚠Experimental
• vmaxv_u32_ 🔒 ^⚠Experimental
• vmaxvq_f32_ 🔒 ^⚠Experimental
• vmaxvq_f64_ 🔒 ^⚠Experimental
• vmaxvq_s8_ 🔒 ^⚠Experimental
• vmaxvq_s16_ 🔒 ^⚠Experimental
• vmaxvq_s32_ 🔒 ^⚠Experimental
• vmaxvq_u8_ 🔒 ^⚠Experimental
• vmaxvq_u16_ 🔒 ^⚠Experimental
• vmaxvq_u32_ 🔒 ^⚠Experimental
• vminv_f32_ 🔒 ^⚠Experimental
• vminv_s8_ 🔒 ^⚠Experimental
• vminv_s16_ 🔒 ^⚠Experimental
• vminv_s32_ 🔒 ^⚠Experimental
• vminv_u8_ 🔒 ^⚠Experimental
• vminv_u16_ 🔒 ^⚠Experimental
• vminv_u32_ 🔒 ^⚠Experimental
• vminvq_f32_ 🔒 ^⚠Experimental
• vminvq_f64_ 🔒 ^⚠Experimental
• vminvq_s8_ 🔒 ^⚠Experimental
• vminvq_s16_ 🔒 ^⚠Experimental
• vminvq_s32_ 🔒 ^⚠Experimental
• vminvq_u8_ 🔒 ^⚠Experimental
• vminvq_u16_ 🔒 ^⚠Experimental
• vminvq_u32_ 🔒 ^⚠Experimental
• vpaddq_s8_ 🔒 ^⚠Experimental
• vpaddq_s16_ 🔒 ^⚠Experimental
• vpaddq_s32_ 🔒 ^⚠Experimental
• vpaddq_s64_ 🔒 ^⚠Experimental
• vpmaxq_f32_ 🔒 ^⚠Experimental
• vpmaxq_f64_ 🔒 ^⚠Experimental
• vpmaxq_s8_ 🔒 ^⚠Experimental
• vpmaxq_s16_ 🔒 ^⚠Experimental
• vpmaxq_s32_ 🔒 ^⚠Experimental
• vpmaxq_u8_ 🔒 ^⚠Experimental
• vpmaxq_u16_ 🔒 ^⚠Experimental
• vpmaxq_u32_ 🔒 ^⚠Experimental
• vpminq_f32_ 🔒 ^⚠Experimental
• vpminq_f64_ 🔒 ^⚠Experimental
• vpminq_s8_ 🔒 ^⚠Experimental
• vpminq_s16_ 🔒 ^⚠Experimental
• vpminq_s32_ 🔒 ^⚠Experimental
• vpminq_u8_ 🔒 ^⚠Experimental
• vpminq_u16_ 🔒 ^⚠Experimental
• vpminq_u32_ 🔒 ^⚠Experimental
• vqtbl1 🔒 ^⚠Experimental
• vqtbl1q 🔒 ^⚠Experimental
• vqtbl2 🔒 ^⚠Experimental
• vqtbl2q 🔒 ^⚠Experimental
• vqtbl3 🔒 ^⚠Experimental
• vqtbl3q 🔒 ^⚠Experimental
• vqtbl4 🔒 ^⚠Experimental
• vqtbl4q 🔒 ^⚠Experimental
• vqtbx1 🔒 ^⚠Experimental
• vqtbx1q 🔒 ^⚠Experimental
• vqtbx2 🔒 ^⚠Experimental
• vqtbx2q 🔒 ^⚠Experimental
• vqtbx3 🔒 ^⚠Experimental
• vqtbx3q 🔒 ^⚠Experimental
• vqtbx4 🔒 ^⚠Experimental
• vqtbx4q 🔒 ^⚠Experimental
• vsli_n_s8_ 🔒 ^⚠Experimental
• vsli_n_s16_ 🔒 ^⚠Experimental
• vsli_n_s32_ 🔒 ^⚠Experimental
• vsli_n_s64_ 🔒 ^⚠Experimental
• vsliq_n_s8_ 🔒 ^⚠Experimental
• vsliq_n_s16_ 🔒 ^⚠Experimental
• vsliq_n_s32_ 🔒 ^⚠Experimental
• vsliq_n_s64_ 🔒 ^⚠Experimental
• vsm3tt1aq_u32^⚠Experimentalneon,sm4
  SM3TT1A
• vsm3tt1bq_u32^⚠Experimentalneon,sm4
  SM3TT1B
• vsm3tt2aq_u32^⚠Experimentalneon,sm4
  SM3TT2A
• vsm3tt2bq_u32^⚠Experimentalneon,sm4
  SM3TT2B
• vsqadd_u8_ 🔒 ^⚠Experimental
• vsqadd_u16_ 🔒 ^⚠Experimental
• vsqadd_u32_ 🔒 ^⚠Experimental
• vsqadd_u64_ 🔒 ^⚠Experimental
• vsqaddq_u8_ 🔒 ^⚠Experimental
• vsqaddq_u16_ 🔒 ^⚠Experimental
• vsqaddq_u32_ 🔒 ^⚠Experimental
• vsqaddq_u64_ 🔒 ^⚠Experimental
• vsri_n_s8_ 🔒 ^⚠Experimental
• vsri_n_s16_ 🔒 ^⚠Experimental
• vsri_n_s32_ 🔒 ^⚠Experimental
• vsri_n_s64_ 🔒 ^⚠Experimental
• vsriq_n_s8_ 🔒 ^⚠Experimental
• vsriq_n_s16_ 🔒 ^⚠Experimental
• vsriq_n_s32_ 🔒 ^⚠Experimental
• vsriq_n_s64_ 🔒 ^⚠Experimental
• vuqadd_s8_ 🔒 ^⚠Experimental
• vuqadd_s16_ 🔒 ^⚠Experimental
• vuqadd_s32_ 🔒 ^⚠Experimental
• vuqadd_s64_ 🔒 ^⚠Experimental
• vuqaddq_s8_ 🔒 ^⚠Experimental
• vuqaddq_s16_ 🔒 ^⚠Experimental
• vuqaddq_s32_ 🔒 ^⚠Experimental
• vuqaddq_s64_ 🔒 ^⚠Experimental
• vxarq_u64^⚠Experimentalneon,sha3
  Exclusive OR and rotate
• vabs_s64^⚠neon
  Absolute Value (wrapping).
• vabsd_s64^⚠neon
  Absolute Value (wrapping).
• vabsq_s64^⚠neon
  Absolute Value (wrapping).
• vadd_f64^⚠neon
  Vector add.
• vadd_s64^⚠neon
  Vector add.
• vadd_u64^⚠neon
  Vector add.
• vaddd_s64^⚠neon
  Vector add.
• vaddd_u64^⚠neon
  Vector add.
• vaddlv_s8^⚠neon
  Signed Add Long across Vector
• vaddlv_u8^⚠neon
  Unsigned Add Long across Vector
• vaddlvq_s8^⚠neon
  Signed Add Long across Vector
• vaddlvq_u8^⚠neon
  Unsigned Add Long across Vector
• vaddq_f64^⚠neon
  Vector add.
• vaddv_s8^⚠neon
  Add across vector
• vaddv_s16^⚠neon
  Add across vector
• vaddv_s32^⚠neon
  Add across vector
• vaddv_u8^⚠neon
  Add across vector
• vaddv_u16^⚠neon
  Add across vector
• vaddv_u32^⚠neon
  Add across vector
• vaddvq_s8^⚠neon
  Add across vector
• vaddvq_s16^⚠neon
  Add across vector
• vaddvq_s32^⚠neon
  Add across vector
• vaddvq_s64^⚠neon
  Add across vector
• vaddvq_u8^⚠neon
  Add across vector
• vaddvq_u16^⚠neon
  Add across vector
• vaddvq_u32^⚠neon
  Add across vector
• vaddvq_u64^⚠neon
  Add across vector
• vbsl_f64^⚠neon
  Bitwise Select instructions. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.
• vbsl_p64^⚠neon
  Bitwise Select.
• vbslq_f64^⚠neon
  Bitwise Select. (128-bit)
• vbslq_p64^⚠neon
  Bitwise Select. (128-bit)
• vcombine_f64^⚠neon
  Vector combine
• vcopy_lane_f64^⚠neon
  Duplicate vector element to vector or scalar
• vcopy_lane_p64^⚠neon
  Duplicate vector element to vector or scalar
• vcopy_lane_s64^⚠neon
  Duplicate vector element to vector or scalar
• vcopy_lane_u64^⚠neon
  Duplicate vector element to vector or scalar
• vcopy_laneq_f64^⚠neon
  Duplicate vector element to vector or scalar
• vcopy_laneq_p64^⚠neon
  Duplicate vector element to vector or scalar
• vcopy_laneq_s64^⚠neon
  Duplicate vector element to vector or scalar
• vcopy_laneq_u64^⚠neon
  Duplicate vector element to vector or scalar
• vdup_n_f64^⚠neon
  Duplicate vector element to vector or scalar
• vdup_n_p64^⚠neon
  Duplicate vector element to vector or scalar
• vdupq_n_f64^⚠neon
  Duplicate vector element to vector or scalar
• vdupq_n_p64^⚠neon
  Duplicate vector element to vector or scalar
• vext_f64^⚠neon
  Extract vector from pair of vectors
• vext_p64^⚠neon
  Extract vector from pair of vectors
• vget_high_f64^⚠neon
  Duplicate vector element to vector or scalar
• vget_high_p64^⚠neon
  Duplicate vector element to vector or scalar
• vget_lane_f64^⚠neon
  Duplicate vector element to vector or scalar
• vget_low_f64^⚠neon
  Duplicate vector element to vector or scalar
• vget_low_p64^⚠neon
  Duplicate vector element to vector or scalar
• vgetq_lane_f64^⚠neon
  Duplicate vector element to vector or scalar
• vld1_dup_f64^⚠neon
  Load multiple single-element structures to one, two, three, or four registers
• vld1_f32^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_f64^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_lane_f64^⚠neon
  Load one single-element structure to one lane of one register.
• vld1_p8^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_p16^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_p64^⚠neon,aes
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_s8^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_s16^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_s32^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_s64^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_u8^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_u16^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_u32^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1_u64^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_dup_f64^⚠neon
  Load multiple single-element structures to one, two, three, or four registers
• vld1q_f32^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_f64^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_lane_f64^⚠neon
  Load one single-element structure to one lane of one register.
• vld1q_p8^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_p16^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_p64^⚠neon,aes
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_s8^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_s16^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_s32^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_s64^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_u8^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_u16^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_u32^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vld1q_u64^⚠neon
  Load multiple single-element structures to one, two, three, or four registers.
• vmaxv_f32^⚠neon
  Horizontal vector max.
• vmaxv_s8^⚠neon
  Horizontal vector max.
• vmaxv_s16^⚠neon
  Horizontal vector max.
• vmaxv_s32^⚠neon
  Horizontal vector max.
• vmaxv_u8^⚠neon
  Horizontal vector max.
• vmaxv_u16^⚠neon
  Horizontal vector max.
• vmaxv_u32^⚠neon
  Horizontal vector max.
• vmaxvq_f32^⚠neon
  Horizontal vector max.
• vmaxvq_f64^⚠neon
  Horizontal vector max.
• vmaxvq_s8^⚠neon
  Horizontal vector max.
• vmaxvq_s16^⚠neon
  Horizontal vector max.
• vmaxvq_s32^⚠neon
  Horizontal vector max.
• vmaxvq_u8^⚠neon
  Horizontal vector max.
• vmaxvq_u16^⚠neon
  Horizontal vector max.
• vmaxvq_u32^⚠neon
  Horizontal vector max.
• vminv_f32^⚠neon
  Horizontal vector min.
• vminv_s8^⚠neon
  Horizontal vector min.
• vminv_s16^⚠neon
  Horizontal vector min.
• vminv_s32^⚠neon
  Horizontal vector min.
• vminv_u8^⚠neon
  Horizontal vector min.
• vminv_u16^⚠neon
  Horizontal vector min.
• vminv_u32^⚠neon
  Horizontal vector min.
• vminvq_f32^⚠neon
  Horizontal vector min.
• vminvq_f64^⚠neon
  Horizontal vector min.
• vminvq_s8^⚠neon
  Horizontal vector min.
• vminvq_s16^⚠neon
  Horizontal vector min.
• vminvq_s32^⚠neon
  Horizontal vector min.
• vminvq_u8^⚠neon
  Horizontal vector min.
• vminvq_u16^⚠neon
  Horizontal vector min.
• vminvq_u32^⚠neon
  Horizontal vector min.
• vmov_n_f64^⚠neon
  Duplicate vector element to vector or scalar
• vmov_n_p64^⚠neon
  Duplicate vector element to vector or scalar
• vmovq_n_f64^⚠neon
  Duplicate vector element to vector or scalar
• vmovq_n_p64^⚠neon
  Duplicate vector element to vector or scalar
• vpaddd_s64^⚠neon
  Add pairwise
• vpaddd_u64^⚠neon
  Add pairwise
• vpaddq_s8^⚠neon
  Add pairwise
• vpaddq_s16^⚠neon
  Add pairwise
• vpaddq_s32^⚠neon
  Add pairwise
• vpaddq_s64^⚠neon
  Add pairwise
• vpaddq_u8^⚠neon
  Add pairwise
• vpaddq_u16^⚠neon
  Add pairwise
• vpaddq_u32^⚠neon
  Add pairwise
• vpaddq_u64^⚠neon
  Add pairwise
• vpmaxq_f32^⚠neon
  Folding maximum of adjacent pairs
• vpmaxq_f64^⚠neon
  Folding maximum of adjacent pairs
• vpmaxq_s8^⚠neon
  Folding maximum of adjacent pairs
• vpmaxq_s16^⚠neon
  Folding maximum of adjacent pairs
• vpmaxq_s32^⚠neon
  Folding maximum of adjacent pairs
• vpmaxq_u8^⚠neon
  Folding maximum of adjacent pairs
• vpmaxq_u16^⚠neon
  Folding maximum of adjacent pairs
• vpmaxq_u32^⚠neon
  Folding maximum of adjacent pairs
• vpminq_f32^⚠neon
  Folding minimum of adjacent pairs
• vpminq_f64^⚠neon
  Folding minimum of adjacent pairs
• vpminq_s8^⚠neon
  Folding minimum of adjacent pairs
• vpminq_s16^⚠neon
  Folding minimum of adjacent pairs
• vpminq_s32^⚠neon
  Folding minimum of adjacent pairs
• vpminq_u8^⚠neon
  Folding minimum of adjacent pairs
• vpminq_u16^⚠neon
  Folding minimum of adjacent pairs
• vpminq_u32^⚠neon
  Folding minimum of adjacent pairs
• vqtbl1_p8^⚠neon
  Table look-up
• vqtbl1_s8^⚠neon
  Table look-up
• vqtbl1_u8^⚠neon
  Table look-up
• vqtbl1q_p8^⚠neon
  Table look-up
• vqtbl1q_s8^⚠neon
  Table look-up
• vqtbl1q_u8^⚠neon
  Table look-up
• vqtbl2_p8^⚠neon
  Table look-up
• vqtbl2_s8^⚠neon
  Table look-up
• vqtbl2_u8^⚠neon
  Table look-up
• vqtbl2q_p8^⚠neon
  Table look-up
• vqtbl2q_s8^⚠neon
  Table look-up
• vqtbl2q_u8^⚠neon
  Table look-up
• vqtbl3_p8^⚠neon
  Table look-up
• vqtbl3_s8^⚠neon
  Table look-up
• vqtbl3_u8^⚠neon
  Table look-up
• vqtbl3q_p8^⚠neon
  Table look-up
• vqtbl3q_s8^⚠neon
  Table look-up
• vqtbl3q_u8^⚠neon
  Table look-up
• vqtbl4_p8^⚠neon
  Table look-up
• vqtbl4_s8^⚠neon
  Table look-up
• vqtbl4_u8^⚠neon
  Table look-up
• vqtbl4q_p8^⚠neon
  Table look-up
• vqtbl4q_s8^⚠neon
  Table look-up
• vqtbl4q_u8^⚠neon
  Table look-up
• vqtbx1_p8^⚠neon
  Extended table look-up
• vqtbx1_s8^⚠neon
  Extended table look-up
• vqtbx1_u8^⚠neon
  Extended table look-up
• vqtbx1q_p8^⚠neon
  Extended table look-up
• vqtbx1q_s8^⚠neon
  Extended table look-up
• vqtbx1q_u8^⚠neon
  Extended table look-up
• vqtbx2_p8^⚠neon
  Extended table look-up
• vqtbx2_s8^⚠neon
  Extended table look-up
• vqtbx2_u8^⚠neon
  Extended table look-up
• vqtbx2q_p8^⚠neon
  Extended table look-up
• vqtbx2q_s8^⚠neon
  Extended table look-up
• vqtbx2q_u8^⚠neon
  Extended table look-up
• vqtbx3_p8^⚠neon
  Extended table look-up
• vqtbx3_s8^⚠neon
  Extended table look-up
• vqtbx3_u8^⚠neon
  Extended table look-up
• vqtbx3q_p8^⚠neon
  Extended table look-up
• vqtbx3q_s8^⚠neon
  Extended table look-up
• vqtbx3q_u8^⚠neon
  Extended table look-up
• vqtbx4_p8^⚠neon
  Extended table look-up
• vqtbx4_s8^⚠neon
  Extended table look-up
• vqtbx4_u8^⚠neon
  Extended table look-up
• vqtbx4q_p8^⚠neon
  Extended table look-up
• vqtbx4q_s8^⚠neon
  Extended table look-up
• vqtbx4q_u8^⚠neon
  Extended table look-up
• vshld_n_s64^⚠neon
  Shift left
• vshld_n_u64^⚠neon
  Shift left
• vshrd_n_s64^⚠neon
  Signed shift right
• vshrd_n_u64^⚠neon
  Unsigned shift right
• vsli_n_p8^⚠neon
  Shift Left and Insert (immediate)
• vsli_n_p16^⚠neon
  Shift Left and Insert (immediate)
• vsli_n_p64^⚠neon,aes
  Shift Left and Insert (immediate)
• vsli_n_s8^⚠neon
  Shift Left and Insert (immediate)
• vsli_n_s16^⚠neon
  Shift Left and Insert (immediate)
• vsli_n_s32^⚠neon
  Shift Left and Insert (immediate)
• vsli_n_s64^⚠neon
  Shift Left and Insert (immediate)
• vsli_n_u8^⚠neon
  Shift Left and Insert (immediate)
• vsli_n_u16^⚠neon
  Shift Left and Insert (immediate)
• vsli_n_u32^⚠neon
  Shift Left and Insert (immediate)
• vsli_n_u64^⚠neon
  Shift Left and Insert (immediate)
• vsliq_n_p8^⚠neon
  Shift Left and Insert (immediate)
• vsliq_n_p16^⚠neon
  Shift Left and Insert (immediate)
• vsliq_n_p64^⚠neon,aes
  Shift Left and Insert (immediate)
• vsliq_n_s8^⚠neon
  Shift Left and Insert (immediate)
• vsliq_n_s16^⚠neon
  Shift Left and Insert (immediate)
• vsliq_n_s32^⚠neon
  Shift Left and Insert (immediate)
• vsliq_n_s64^⚠neon
  Shift Left and Insert (immediate)
• vsliq_n_u8^⚠neon
  Shift Left and Insert (immediate)
• vsliq_n_u16^⚠neon
  Shift Left and Insert (immediate)
• vsliq_n_u32^⚠neon
  Shift Left and Insert (immediate)
• vsliq_n_u64^⚠neon
  Shift Left and Insert (immediate)
• vsqadd_u8^⚠neon
  Unsigned saturating Accumulate of Signed value.
• vsqadd_u16^⚠neon
  Unsigned saturating Accumulate of Signed value.
• vsqadd_u32^⚠neon
  Unsigned saturating Accumulate of Signed value.
• vsqadd_u64^⚠neon
  Unsigned saturating Accumulate of Signed value.
• vsqaddq_u8^⚠neon
  Unsigned saturating Accumulate of Signed value.
• vsqaddq_u16^⚠neon
  Unsigned saturating Accumulate of Signed value.
• vsqaddq_u32^⚠neon
  Unsigned saturating Accumulate of Signed value.
• vsqaddq_u64^⚠neon
  Unsigned saturating Accumulate of Signed value.
• vsrad_n_s64^⚠neon
  Signed shift right and accumulate
• vsrad_n_u64^⚠neon
  Unsigned shift right and accumulate
• vsri_n_p8^⚠neon
  Shift Right and Insert (immediate)
• vsri_n_p16^⚠neon
  Shift Right and Insert (immediate)
• vsri_n_p64^⚠neon,aes
  Shift Right and Insert (immediate)
• vsri_n_s8^⚠neon
  Shift Right and Insert (immediate)
• vsri_n_s16^⚠neon
  Shift Right and Insert (immediate)
• vsri_n_s32^⚠neon
  Shift Right and Insert (immediate)
• vsri_n_s64^⚠neon
  Shift Right and Insert (immediate)
• vsri_n_u8^⚠neon
  Shift Right and Insert (immediate)
• vsri_n_u16^⚠neon
  Shift Right and Insert (immediate)
• vsri_n_u32^⚠neon
  Shift Right and Insert (immediate)
• vsri_n_u64^⚠neon
  Shift Right and Insert (immediate)
• vsriq_n_p8^⚠neon
  Shift Right and Insert (immediate)
• vsriq_n_p16^⚠neon
  Shift Right and Insert (immediate)
• vsriq_n_p64^⚠neon,aes
  Shift Right and Insert (immediate)
• vsriq_n_s8^⚠neon
  Shift Right and Insert (immediate)
• vsriq_n_s16^⚠neon
  Shift Right and Insert (immediate)
• vsriq_n_s32^⚠neon
  Shift Right and Insert (immediate)
• vsriq_n_s64^⚠neon
  Shift Right and Insert (immediate)
• vsriq_n_u8^⚠neon
  Shift Right and Insert (immediate)
• vsriq_n_u16^⚠neon
  Shift Right and Insert (immediate)
• vsriq_n_u32^⚠neon
  Shift Right and Insert (immediate)
• vsriq_n_u64^⚠neon
  Shift Right and Insert (immediate)
• vst1_f32^⚠neon
• vst1_f64^⚠neon
• vst1_p8^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1_p16^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1_p64^⚠neon,aes
  Arm’s documentation
• vst1_s8^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1_s16^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1_s32^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1_s64^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1_u8^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1_u16^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1_u32^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1_u64^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1q_f32^⚠neon
• vst1q_f64^⚠neon
• vst1q_p8^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1q_p16^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1q_p64^⚠neon,aes
  Arm’s documentation
• vst1q_s8^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1q_s16^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1q_s32^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1q_s64^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1q_u8^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1q_u16^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1q_u32^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vst1q_u64^⚠neon
  Store multiple single-element structures from one, two, three, or four registers.
• vtbl1_p8^⚠neon
  Table look-up
• vtbl1_s8^⚠neon
  Table look-up
• vtbl1_u8^⚠neon
  Table look-up
• vtbl2_p8^⚠neon
  Table look-up
• vtbl2_s8^⚠neon
  Table look-up
• vtbl2_u8^⚠neon
  Table look-up
• vtbl3_p8^⚠neon
  Table look-up
• vtbl3_s8^⚠neon
  Table look-up
• vtbl3_u8^⚠neon
  Table look-up
• vtbl4_p8^⚠neon
  Table look-up
• vtbl4_s8^⚠neon
  Table look-up
• vtbl4_u8^⚠neon
  Table look-up
• vtbx1_p8^⚠neon
  Extended table look-up
• vtbx1_s8^⚠neon
  Extended table look-up
• vtbx1_u8^⚠neon
  Extended table look-up
• vtbx2_p8^⚠neon
  Extended table look-up
• vtbx2_s8^⚠neon
  Extended table look-up
• vtbx2_u8^⚠neon
  Extended table look-up
• vtbx3_p8^⚠neon
  Extended table look-up
• vtbx3_s8^⚠neon
  Extended table look-up
• vtbx3_u8^⚠neon
  Extended table look-up
• vtbx4_p8^⚠neon
  Extended table look-up
• vtbx4_s8^⚠neon
  Extended table look-up
• vtbx4_u8^⚠neon
  Extended table look-up
• vuqadd_s8^⚠neon
  Signed saturating Accumulate of Unsigned value.
• vuqadd_s16^⚠neon
  Signed saturating Accumulate of Unsigned value.
• vuqadd_s32^⚠neon
  Signed saturating Accumulate of Unsigned value.
• vuqadd_s64^⚠neon
  Signed saturating Accumulate of Unsigned value.
• vuqaddq_s8^⚠neon
  Signed saturating Accumulate of Unsigned value.
• vuqaddq_s16^⚠neon
  Signed saturating Accumulate of Unsigned value.
• vuqaddq_s32^⚠neon
  Signed saturating Accumulate of Unsigned value.
• vuqaddq_s64^⚠neon
  Signed saturating Accumulate of Unsigned value.